Hardware Club

[paul]

[...] Today’s announcement isn’t just that our new Gate-All-Around (GAA) nanosheet device architecture enables us to fit 50 billion transistors in a space roughly the size of a fingernail. It’s not just that IBM Research’s second-generation nanosheet technology has paved a path to the 2-nanometer (nm) node. Or that we produced this breakthrough technology on a 300 millimeter (mm) wafer built at IBM Research’s semiconductor research facility in Albany, NY. [...]

This second iteration of our nanosheet transistor architecture involves a new type of horizontally stacked GAA chip design. Four “gates” on a transistor enable superior electrical signals to pass through and between other transistors on a chip. [...]

Put in perspective, 2 nm processors used in cell phones could quadruple the battery life of cell phones using 7 nm process technology, such as the iPhone 11, Samsung Galaxy S10 and Google Pixel 5. Based on average use, this means the phone would only need to be charged once every four days.

Scaling to the 2 nm chip node transistor equates to an approximate 45 percent performance improvement over today’s 7 nm chips, using the same amount of power. That’s an approximate 75 percent power savings, at the same performance level. This kind of power/performance combination is essential to accelerating the development and delivery of advanced cognitive, edge and other computing platforms delivered via hybrid cloud environments, as well as encryption accelerators built to operate with quantum computers.

IBM Research continues to explore options for continued scaling to 1 nm and beyond. [...]

Although we’re still several years away from manufacturing of 2 nm node devices, IBM Research’s innovations feed directly into our commercial product roadmap. [...]

Our 2 nm chip: the sum of several “Aha!” moments | IBM Research Blog